1. Field of the Invention
The present invention generally relates to semiconductor memories and, more particularly, to a series of array structures, arrangements, and activation schemes for high density, fast access semiconductor memories that have a separate read and write data line and that exhibit destructive write behavior.
2. Discussion of Background
In conventional microprocessors, a cache memory module is fabricated on the same semiconductor die as the processing logic in order to accommodate rapid data and instruction storage and retrieval. Semiconductor memories for on-chip cache applications are typically comprised of six-transistor static random access memory (6T SRAM) or one-transistor one-capacitor dynamic random access memory (1T-1C DRAM). The 6T cell is the more common solution since the access speed is faster and design and production costs are low since the memory can be fabricated next to the logic with a minimal addition in processing steps. However, as cache memory capacity requirements greatly increase to accommodate for multimedia processing, the large cell size of the 6T SRAM leads to a large area, high cost cache memory solution.
A 1T-1C DRAM memory cell can be used as a semiconductor memory when high bit density is required. This technology has several drawbacks and faces serious complications as device dimensions are scaled smaller. Notably, since the DRAM cell has no internal gain, a high capacitance element (˜30 fF) must be fabricated in each cell to store a charge large enough to be reliably detected. Therefore, complex capacitor structures and expensive materials must be used to build a device with adequate capacitance, which leads to expensive fabrication and incompatibilities with standard logic processes.
Inexpensive gain cell technologies (for example, three transistor (3T) memory cell technologies) with bit densities much larger than SRAM have been proposed to provide high-density cache memories. However, these often fail to be used in products because of a slower access time than SRAM. In a conventional destructive write dual data line gain cell memory, the output of the sense amplifier of the read data line signal is directly connected to the write data line. A write access proceeds as follows. Data is first read from all cells in the selected row by activating the read word line and discriminating the data with a sense amplifier. New data presented to the bank is written over the old data only in the selected columns. A data write phase then occurs in which the data in the sense amplifiers is applied to the write data line and the write word line is activated, transferring the new data to the selected cells. In this manner, the write cycle time is the summation of the read and write phases. This long read then write cycle is a serious detriment to gain cell solutions, especially those with a longer write phase.
For solving the above problems, a 3T memory cell technology written in JP10-134565 proposes. FIG. 3 shows a part of the FIG. 1 of JP10-134565. The 3T memory cell of FIG. 3 separates write word line and uses AND logic of write word line signal WWL and column select signal WY for selecting the write word line. In this way the write operation can become a non-destruction operation because the number of memory cells selected by the write word line is equal to the number of data written to memory cells. Therefore it does not need to read the data from the memory cells selected by write word line and high speed write operation can be realized.
Although it is efficient to use this technology in writing a lot of bits of data, it is difficult to adopt this technology in writing small bits of data, for example 8 bit data. The reason of this is because it needs to separate the write word line every 8 bit, the region of AND circuit for selecting the write word line and wiring of the column select signal increases. Therefore the feature of 3T memory cell that is high density is damaged.